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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. DSLVDS1048 snls624 ? september 2018 DSLVDS1048 3.3-v lvds quad channel high-speed differential line receiver 1 1 features 1 ? designed for signal rates up to 400 mbps ? flow-through pinout simplifies pcb layout ? 150-ps channel-to-channel skew (typical) ? 100-ps differential skew (typical) ? 2.7-ns maximum propagation delay ? 3.3-v power supply design ? high impedance lvds inputs on power down ? low power design (40 mw at 3.3-v static) ? interoperable with existing 5-v lvds drivers ? accepts small swing (350 mv typical) differential signal levels ? supports input failsafe ? open, short, and terminated ? 0 v to ? 100 mv threshold region ? operating temperature range: ? 40 c to +85 c ? meets or exceeds ansi/tia/eia-644 standard ? available in tssop package 2 applications ? multifunction printers ? board-to-board communication ? test and measurement ? printers ? data center interconnect ? lab instrumentation ? ultrasound scanners 3 description the DSLVDS1048 device is a quad cmos flow- through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. the device is designed to support data rates in excess of 400 mbps (200 mhz) using low voltage differential signaling (lvds) technology. the DSLVDS1048 accepts low voltage (350 mv typical) differential input signals and translates them to 3-v cmos output levels. the receiver supports a tri-state function that may be used to multiplex outputs. the receiver also supports open, shorted, and terminated (100- ) input fail-safe. the receiver output is high for all fail-safe conditions. the DSLVDS1048 has a flow-through pinout for easy pcb layout. the en and en* inputs are anded together and control the tri-state outputs. the enables are common to all four receivers. the DSLVDS1048 and companion lvds line driver (for example, dslvds1047) provide a new alternative to high- power pecl/ecl devices for high-speed point-to- point interface applications. device information (1) part number package body size (nom) DSLVDS1048 tssop (16) 5.00 mm 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. figure 1. application diagram productfolder receiver driver d in1 d out1+ dslvds1047 receiver driver receiver driver receiver driver d in2 d in3 d in4 d out2+ d out3+ d out4+ d out1- d out2- d out3- d out4- en en* r in1+ r in1- r in2+ r in2- r in3+ r in3- r in4+ r in4- r out1 r out2 r out3 r out4 100 100 100 en en* 100 DSLVDS1048 support &community tools & software technical documents ordernow
2 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 3 6.1 absolute maximum ratings ...................................... 3 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 4 6.6 switching characteristics .......................................... 5 6.7 typical characteristics .............................................. 6 7 parameter measurement information .................. 9 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 11 8.4 device functional modes ........................................ 11 9 application and implementation ........................ 12 9.1 application information ............................................ 12 9.2 typical application ................................................. 12 10 power supply recommendations ..................... 14 11 layout ................................................................... 14 11.1 layout guidelines ................................................. 14 11.2 layout example .................................................... 15 12 device and documentation support ................. 16 12.1 receiving notification of documentation updates 16 12.2 community resources .......................................... 16 12.3 trademarks ........................................................... 16 12.4 electrostatic discharge caution ............................ 16 12.5 glossary ................................................................ 16 13 mechanical, packaging, and orderable information ........................................................... 17 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes september 2018 * initial release.
3 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions pw package 16-pin tssop top view pin functions pin i/o description name no. en 16 i receiver enable pin: when en is low, the receiver is disabled. when en is high and en* is low or open, the receiver is enabled. if both en and en* are open circuit, then the receiver is disabled. en* 9 i receiver enable pin: when en* is high, the receiver is disabled. when en* is low or open and en is high, the receiver is enabled. if both en and en* are open circuit, then the receiver is disabled. gnd 12 ? ground pin r in+ 2, 3, 6, 7 i noninverting receiver input pin r in ? 1, 4, 5, 8 i inverting receiver input pin r out 10, 11, 14, 15 o receiver output pin v cc 13 ? power supply pin, +3.3v 0.3v (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. 6 specifications 6.1 absolute maximum ratings see (1) (2) min max unit supply voltage (v cc ) ? 0.3 4 v input voltage (r in+ , r in ? ) ? 0.3 3.6 v enable input voltage (en, en*) ? 0.3 v cc + 0.3 v output voltage (r out ) ? 0.3 v cc + 0.3 v maximum package power dissipation at +25 c pw0016a package 866 mw derate pw0016a package above +25 c 6.9 mw/ c lead temperature soldering (4 s) 260 c maximum junction temperature 150 c storage temperature, t stg ? 65 150 c
4 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) esd rating: hbm (1.5 k , 100 pf) eiaj (0 , 200 pf) 6.2 esd ratings value unit v (esd) electrostatic discharge (1) human-body model (hbm) 10000 v machine model 1200 6.3 recommended operating conditions min nom max unit supply voltage, v cc 3 3.3 3.6 v receiver input voltage gnd 3 v operating free air temperature, t a ? 40 25 85 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) DSLVDS1048 unit pw (tssop) 16 pins r ja junction-to-ambient thermal resistance 110.2 c/w r jc(top) junction-to-case (top) thermal resistance 47 c/w r jb junction-to-board thermal resistance 54.7 c/w jt junction-to-top characterization parameter 6.1 c/w jb junction-to-board characterization parameter 54.2 c/w (1) current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground unless otherwise specified. (2) all typicals are given for: v cc = 3.3 v, t a = 25 c. (3) v cc is always higher than r in+ and r in ? voltage. r in ? and r in+ are allowed to have a voltage range ? 0.2 v to v cc ? vid/2. however, to be compliant with ac specifications, the common voltage range is 0.1 v to 2.3 v. (4) the vcmr range is reduced for larger vid. example: if vid = 400 mv, the vcmr is 0.2 v to 2.2 v. the fail-safe condition with inputs shorted is not supported over the common-mode range of 0 v to 2.4 v, but is supported only with inputs shorted and no external common-mode voltage applied. a vid up to v cc ? 0 v may be applied to the r in+ / r in ? inputs with the common-mode voltage set to v cc /2. propagation delay and differential pulse skew decrease when vid is increased from 200 mv to 400 mv. skew specifications apply for 200 mv vid 800 mv over the common-mode range. (5) output short-circuit current (i os ) is specified as magnitude only; minus sign indicates direction only. only one output should be shorted at a time; do not exceed maximum junction temperature specification. 6.5 electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) parameter test conditions pin min typ max unit v th differential input high threshold v cm = +1.2 v, 0.05 v, 2.95 v (3) r in+ , r in ? 100 mv v tl differential input low threshold ? 100 mv vcmr common-mode voltage range vid = 200 mv peak to peak? (4) 0.1 2.3 v i in input current v in = +2.8 v v cc = 3.6 v or 0 v ? 10 5 10 a v in = 0 v ? 10 1 10 v in = +3.6 v v cc = 0 v ? 20 1 20 v oh output high voltage i oh = ? 0.4 ma, v id = +200 mv, input terminated, input shorted r out 2.7 3.3 v v ol output low voltage i ol = 2 ma, v id = ? 200 mv 0.25 v i os output short-circuit current enabled, v out = 0 v (5) ? 15 ? 47 ? 100 ma i oz output tri-state current disabled, v out = 0 v or v cc ? 10 1 10 a
5 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) parameter test conditions pin min typ max unit v ih input high voltage en, en* 2 v cc v v il input low voltage gnd 0.8 v i i input current v in = 0 v or v cc , other input = v cc or gnd ? 10 5 10 a v cl input clamp voltage i cl = ? 18 ma ? 1.5 ? 0.8 v i cc no load supply current receivers enabled en = v cc , inputs open v cc 9 15 ma i ccz no load supply current receivers disabled en = gnd, inputs open 1 5 ma (1) all typicals are given for: v cc = 3.3 v, t a = 25 c. (2) generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50 , t r and t f (0% to 100%) 3 ns for r in . (3) t skd2 , channel-to-channel skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. (4) t skd3 , part-to-part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to devices at the same v cc , and within 5 c of each other within the operating temperature range. (5) t skd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel (6) t skd4 , part-to-part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t skd4 is defined as |max ? min| differential propagation delay. (7) f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05-v to 1.35-v peak to peak). output criteria: 60 / 40% duty cycle, v ol (maximum 0.4 v), v oh (minimum 2.7 v), load = 15 pf (stray plus probes). 6.6 switching characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) (2) (3) (4) parameter test conditions min typ max unit t phld differential propagation delay high to low c l = 15 pf v id = 200 mv ( figure 16 and figure 17 ) 1.2 2 2.7 ns t plhd differential propagation delay low to high 1.2 2 2.7 ns t skd1 differential pulse skew |t phld ? t plhd | (5) 0.1 0.4 ns t skd2 differential channel-to-channel skew; same device (3) 0.15 0.5 ns t skd3 differential part-to-part skew (4) 1 ns t skd4 differential part-to-part skew (6) 1.5 ns t tlh rise time 0.5 1 ns t thl fall time 0.5 1 ns t phz disable time high to z r l = 2 k ? c l = 15 pf ( figure 18 and figure 19 ) 8 14 ns t plz disable time low to z 8 14 ns t pzh enable time z to high 9 14 ns t pzl enable time z to low 9 14 ns f max maximum operating frequency (7) all channels switching 200 250 mhz
6 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 typical characteristics figure 2. output high voltage vs power supply voltage figure 3. output low voltage vs power supply voltage figure 4. output short-circuit current vs power supply voltage figure 5. output tri-state current vs power supply voltage figure 6. differential transition voltage vs power supply voltage figure 7. power supply current vs ambient temperature
7 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) figure 8. differential propagation delay vs power supply voltage figure 9. differential propagation delay vs ambient temperature figure 10. differential propagation delay vs differential input voltage figure 11. differential propagation delay vs common-mode voltage figure 12. differential skew vs power supply voltage figure 13. differential skew vs ambient temperature
8 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) figure 14. transition time vs power supply voltage figure 15. transition time vs ambient temperature
9 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information figure 16. receiver propagation delay and transition time test circuit figure 17. receiver propagation delay and transition time waveforms c l includes load and test jig capacitance. s 1 = v cc for t pzl and t plz measurements. s 1 = gnd for t pzh and t phz measurements. figure 18. receiver tri-state delay test circuit figure 19. receiver tri-state delay waveforms
10 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview lvds drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as shown in figure 20 . this configuration provides a clean signaling environment for the fast edge rates of the drivers. the receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply pcb traces. typically, the characteristic impedance of the media is in the range of 100 . a termination resistor of 100 (selected to match the media) is located as close to the receiver input pins as possible. the termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be considered. the DSLVDS1048 differential line receiver is capable of detecting signals as low as 100 mv, over a 1-v common-mode range centered around +1.2 v. this is related to the driver offset voltage which is typically +1.2 v. the driven signal is centered around this voltage and may shift 1 v around this center point. the 1-v shifting may be the result of a ground potential difference between the ground reference of the driver and the ground reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. the ac parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 v to +2.4 v (measured from each pin to ground). the device operates for receiver input voltages up to v cc , but exceeding v cc turns on the esd protection circuitry, which clamps the bus voltages. the DSLVDS1048 has a flow-through pinout that allows for easy pcb layout. the lvds signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. noise isolation is achieved with the lvds signals on one side of the device and the ttl signals on the other side. 8.2 functional block diagram
11 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 feature description 8.3.1 fail-safe feature the lvds receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mv) to cmos logic levels. due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal. the internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating, terminated or shorted receiver inputs. 1. open input pins. the DSLVDS1048 is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused channel(s) inputs must be left open. do not tie unused receiver inputs to ground or any other voltages. the input is biased by internal high value pullup and pulldown resistors to set the output to a high state. this internal circuitry ensures a high, stable output state for open inputs. 2. terminated input. if the driver is disconnected (cable unplugged), or if the driver is in a tri-state or power-off condition, the receiver output is again in a high state, even with the end of cable 100- termination resistor across the input pins. the unplugged cable can become a floating antenna which can pick up noise. if the cable picks up more than 10 mv of differential noise, the receiver may see the noise as a valid signal and switch. to ensure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. twisted pair cable offers better balance than flat ribbon cable. 3. shorted inputs. if a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-v differential input voltage, the receiver output remains in a high state. shorted input fail-safe is not supported across the common-mode range of the device (gnd to 2.4 v). it is only supported with inputs shorted and no external common-mode voltage applied. external lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. the pullup and pulldown resistors must be in the 5-k ? to 15-k ? range to minimize loading and waveform distortion to the driver. the common-mode bias point must be set to approximately 1.2 v (less than 1.75 v) to be compatible with the internal circuitry. additional information on fail-safe biasing of lvds devices may be found in an-1194 failsafe biasing of lvds interfaces (snla051). 8.4 device functional modes table 1 lists the functional modes of the DSLVDS1048. table 1. truth table enables input output en en* r in+ ? r in ? r out h l or open v id 0 v h v id ? 0.1 v l full fail-safe open/short or terminated h all other combinations of enable inputs x z
12 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the DSLVDS1048 has a flow-through pinout that allows for easy pcb layout. the lvds signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. noise isolation is achieved with the lvds signals on one side of the device and the ttl signals on the other side. 9.2 typical application figure 20. balanced system point-to-point application receiver driver d in1 d out1+ dslvds1047 receiver driver receiver driver receiver driver d in2 d in3 d in4 d out2+ d out3+ d out4+ d out1- d out2- d out3- d out4- en en* r in1+ r in1- r in2+ r in2- r in3+ r in3- r in4+ r in4- r out1 r out2 r out3 r out4 100 100 100 en en* 100 DSLVDS1048
13 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 9.2.1 design requirements when using lvds devices, it is important to remember to specify controlled impedance pcb traces, cable assemblies, and connectors. all components of the transmission media must have a matched differential impedance of about 100 . they must not introduce major impedance discontinuities. balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. balanced cables tend to generate less emi due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the lvds receiver. for cable distances < 0.5 m, most cables can be made to work effectively. for distances 0.5 m d 10 m, cat5 (category 5) twisted pair cable works well, is readily available, and relatively inexpensive. table 2. design requirements design parameters example value receiver supply voltage (v cc ) 3.0 to 3.6 v receiver output voltage 0 to 3.6 v signaling rate 0 to 400 mbps interconnect characteristic impedance 100 termination resistance 100 number of receiver nodes 1 ground shift between driver and receiver 1 v 9.2.2 detailed design procedure 9.2.2.1 probing lvds transmission lines always use high impedance ( > 100k ? ), low capacitance ( < 2 pf) scope probes with a wide bandwidth (1 ghz) scope. improper probing gives deceiving results. 9.2.2.2 threshold the lvds standard (ansi/tia/eia-644) specifies a maximum threshold of 100 mv for the lvds receiver. the DSLVDS1048 supports an enhanced threshold region of ? 100 mv to 0 v. this is useful for fail-safe biasing. the threshold region is shown in the voltage transfer curve (vtc) in figure 21 . the typical DSLVDS1048 lvds receiver switches at about ? 35 mv. note with v id = 0 v, the output is in a high state. with an external fail-safe bias of +25 mv applied, the typical differential noise margin is now the difference from the switch point to the bias point. in the following example, this would be 60 mv of differential noise margin (+25 mv ? ( ? 35 mv)). with the enhanced threshold region of ? 100 mv to 0 v, this small external fail-safe biasing of +25 mv (with respect to 0 v) gives a dnm of a comfortable 60 mv. with the standard threshold region of 100 mv, the external fail-safe biasing would need to be +25 mv with respect to +100 mv or +125 mv, giving a dnm of 160 mv which is stronger fail-safe biasing than is necessary for the DSLVDS1048. if more dnm is required, then a stronger fail- safe bias point can be set by changing resistor values.
14 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 21. vtc of the DSLVDS1048 lvds receiver 9.2.3 application curve figure 22. power supply current vs frequency 10 power supply recommendations although the dslvds1047 draws very little power while at rest, its overall power consumption increases due to a dynamic current component. the DSLVDS1048 power supply connection must take this additional current consumption into consideration for maximum power requirements. 11 layout 11.1 layout guidelines ? use at least 4 pcb layers (top to bottom): lvds signals, ground, power, and ttl signals. ? isolate ttl signals from lvds signals, otherwise the ttl may couple onto the lvds lines. best practice is to put ttl and lvds signals on different layers which are isolated by a power/ground plane(s). ? keep drivers and receivers as close to the (lvds port side) connectors as possible. 11.1.1 power decoupling recommendations bypass capacitors must be used on power pins. use high-frequency ceramic (surface mount is recommended) 0.1- f and 0.001- f capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. additional scattered capacitors over the printed-circuit board improves decoupling. multiple vias must be used to connect the decoupling capacitors to the power planes. a 10- f (35-v) or greater solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply and ground.
15 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) 11.1.2 differential traces use controlled impedance traces that match the differential impedance of your transmission medium (that is, cable) and termination resistor. run the differential pair trace lines as close together as possible as soon as they leave the ic (stubs must be < 10 mm long). this helps eliminate reflections and ensure noise is coupled as common-mode. in fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart because magnetic field cancellation is much better with the closer traces. in addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. match electrical lengths between traces to reduce skew. skew between the signals of a pair means a phase difference between signals, which destroys the magnetic field cancellation benefits of differential signals and emi, results. remember the velocity of propagation, v = c/er where c (the speed of light) = 0.2997 mm/ps or 0.0118 in/ps. do not rely solely on the autoroute function for differential traces. carefully review dimensions to match differential impedance and provide isolation for the differential lines. minimize the number or vias and other discontinuities on the line. avoid 90 turns (these cause impedance discontinuities). use arcs or 45 bevels. within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. on the printed-circuit board, this distance must remain constant to avoid discontinuities in differential impedance. minor violations at connection points are allowable. 11.1.3 termination use a termination resistor that best matches the differential impedance or your transmission line. the resistor must be between 90 ? and 130 ? . remember that the current mode outputs need the termination resistor to generate the differential voltage. lvds does not work without resistor termination. typically, connecting a single resistor across the pair at the receiver end will suffice. surface mount 1% to 2% resistors are best. pcb stubs, component lead, and the distance from the termination to the receiver inputs must be minimized. the distance between the termination resistor and the receiver must be < 10 mm (12 mm maximum). 11.2 layout example figure 23. layout recommendation 8 7 decoupling cap 6 5 4 3 2 1 9 10 11 12 13 14 15 16 v cc d in2 d in1 en d in3 d in4 en* gnd d out4- d out4+ d out3+ d out3- d out2- d out2+ d out1+ d out1- ds90lv047a 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 r out2 r out1 en r out3 r out4 en* gnd ds90lv048a r in4- r in4+ r in3+ r in3- r in2- r in2+ r in1+ r in1- lvcmos inputs v cc decoupling cap series termination (optional) series termination (optional) lvcmos outputs input termination (required)
16 DSLVDS1048 snls624 ? september 2018 www.ti.com product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
17 DSLVDS1048 www.ti.com snls624 ? september 2018 product folder links: DSLVDS1048 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 28-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DSLVDS1048pwr preview tssop pw 16 2500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 dslvds 1048 DSLVDS1048pwt preview tssop pw 16 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 dslvds 1048 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 28-sep-2018 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DSLVDS1048pwr tssop pw 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 28-sep-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DSLVDS1048pwr tssop pw 16 2500 367.0 367.0 35.0 package materials information www.ti.com 28-sep-2018 pack materials-page 2
www.ti.com package outline c 14x 0.65 2x 4.55 16x 0.30 0.19 typ 6.6 6.2 1.2 max 0.15 0.05 0.25 gage plane -8 0 b note 4 4.5 4.3 a note 3 5.1 4.9 0.75 0.50 (0.15) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 1 8 9 16 0.1 c a b pin 1 index area see detail a 0.1 c notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm per side. 5. reference jedec registration mo-153. seating plane a 20 detail a typical scale 2.500
www.ti.com example board layout 0.05 max all around 0.05 min all around 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. land pattern example exposed metal shown scale: 10x symm symm 1 8 9 16 15.000 metal solder mask opening metal under solder mask solder mask opening exposed metal exposed metal solder mask details non-solder mask defined (preferred) solder mask defined
www.ti.com example stencil design 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale: 10x symm symm 1 8 9 16
important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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